1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device and a power line arrangement method thereof.
2. Description of the Prior Art
Power lines of a conventional semiconductor memory device are arranged on two layers like signal lines. The power lines on a first layer and the power lines on a second layer are arranged in perpendicular direction to each other to make grid-shape connections because the electrical power can be more stably supplied via grid-shape connections.
Among the power lines of the conventional semiconductor memory device, some power lines may be directly supplied with the electrical power from a power supply input pad. In such instance, the power lines which are supplied with electrical power from the pad form grid-shape connections, but the pad just functions to supply the electrical power and does not form the grid-shape connections together with the power lines.
FIG. 1 is a schematic diagram illustrating a power line arrangement method of a conventional semiconductor memory device. In FIG. 1, reference numerals 10, 20, 30, and 40 denote a memory cell array, a row decoder, a column decoder, and a data control and internal voltage generator, respectively.
In FIG. 1, non-hatched lines denote power lines arranged on a first layer, hatched lines denote power lines arranged on a second layer, and “PVDD” and “PVSS” denote power voltage applying pads and ground voltage applying pads, respectively.
The lower line arrangement method of the conventional semiconductor memory device will be explained below with reference to FIG. 1.
In the first layer, array power lines AP1 are arranged in a longitudinal direction above the memory cell array 10, peripheral circuit power lines PPVDD1 and PPVSS1 are arranged in a longitudinal direction above the row decoder 20, and peripheral circuit power lines PPVDD1 and PPVSS1 are arranged in a transverse direction above the column decoder 30 and the data control and internal voltage generator 40, respectively.
In the second layer, array power lines AP2 are arranged above the memory cell array 10 in a perpendicular direction to the array power lines AP1; peripheral circuit power lines PPVDD2 and PPVSS2 are arranged above the row decoder 20 in a perpendicular direction to the peripheral circuit power lines PPVDD1 and PPVSS1; and peripheral circuit power lines PPVDD2 and PPVSS2 are arranged above the column decoder 30 and the data control and internal power voltage generator 40 in a perpendicular direction to the peripheral circuit power lines PPVDD1 and PPVSS1. In the second layer, subperipheral circuit power lines PPVDD2′ and PPVSS2′ extend respectively from pads PVDD and PVSS to be connected to the peripheral circuit power lines PPVDD1 and PPVSS1, and a subperipheral circuit power line PPVSS2′ extends from the pad PVSS to be connected to the peripheral circuit power line PPVSS2.
FIG. 2A is a plan view illustrating the pad of FIG. 1, and FIG. 2B is a cross-sectional view taken along line X-X′ of FIG. 2A.
As shown in FIG. 2B, the pad includes a dummy portion and a signal line portion. The dummy portion includes a dummy diffusion layer, an insulating layer, and a dummy polysilicon layer for matching a step height with the memory cell array 10 and a peripheral circuit. Here, the peripheral circuit includes the row decoder 20, the column decoder 30, and the data control and internal voltage generator 40 except the memory cell array 10. The signal line portion includes a lower metal pad DPAD arranged on a first layer 1F and an upper metal pad UPAD arranged on a second layer 2F. A conductive layer COD is arranged between the lower and upper metal pads DPAD and UPAD to electrically connect the lower and upper metal pads DPAD and UPAD to each other. The conductive layer COD is formed using a technique for forming a contact. That is, the pad includes the upper metal pad UPAD, the conductive layer COD and the lower metal pad DPAD which are arranged in the signal line portion, and the lower metal pad DPAD functions to absorb an impact which may occur when the conductive layer COD is formed.
As shown in FIG. 2B, the pad of the conventional memory device includes two layers: the upper metal pad UPAD which is directly supplied with the electrical power externally applied and the lower metal pad DPAD which absorbs an impact when the conductive layer is formed.
In general, as the number of grid-shape connections is increased, the electrical power can be more stably supplied, but the conventional semiconductor memory device has a disadvantage in that it is difficult to make a connection between the pads. That is, if the power voltage applying pad PVDD and the ground voltage applying pad PVSS are alternately arranged as shown in FIG. 1, it is impossible to make connection between the pads PVDD which apply a voltage of the same level due to the pad power line PVSS2 arranged on the second layer. Thus, since there are no connections between the power voltage applying pads PVDD and between the ground voltage applying pads PVSS, more stable electrical power can not be supplied.
On the other hand, unlike FIG. 1, if the power voltage applying pads PVDD are arranged concentrically on one side and the power voltage applying pads PVSS are arranged concentrically on the other side, it is possible to make connection between the power voltage applying pads PVDD. However, this arrangement requires a space between the pads PVDD and PVSS and the row decoder 20 for making connections between the power voltage applying pads PVDD and between the ground voltage applying pads PVSS, leading to increased layout area size of the semiconductor memory device.